`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:34:25 08/28/2012
// Design Name:   walk_register
// Module Name:   C:/Users/maye/Desktop/alle archivos/lab2/walk_register_prueba.v
// Project Name:  lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: walk_register
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module walk_register_prueba;

	// Inputs
	reg clk_i;
	reg reset;
	reg walk_i;
	reg walk_reset;

	// Outputs
	wire walk_o;

	// Instantiate the Unit Under Test (UUT)
	walk_register uut (
		.clk_i(clk_i), 
		.reset(reset), 
		.walk_i(walk_i), 
		.walk_o(walk_o), 
		.walk_reset(walk_reset)
	);
	
	always begin 
	 #50 clk_i=~clk_i;
	end

	initial begin
		// Initialize Inputs
		clk_i = 0;
		reset = 0;
		walk_i = 0;
		walk_reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
		walk_i = 1;
      

		#100;
		walk_i = 0;
		
		#100;
		walk_reset = 1;
		// Add stimulus here

	end
      
endmodule

